Programmable units with a two- or multi-dimensional cell architecture (in particular FPGAs, DPGAs and DFPs, etc.) are programmed today in two different ways.                Once, i.e., the configuration cannot be changed after programming. All the configured elements of the unit thus perform the same function over the entire period of time during which the application is being carried out.        During operation, i.e., the configuration can be changed after installation of the unit, by loading a configuration data file, at the start of the application. Units such as, for example, FPGA units, cannot be reconfigured during operation. With reconfigurable units, further processing of data during the reconfiguration is usually impossible, and the required reconfiguration time is much too long.        
In addition to FPGAs, there are also DPGAs. These units store a number of different configurations which are selected by a special data packet. Run-time reconfiguration of these memory devices is impossible.
Major problems are posed by run-time reconfiguration of all programmable units or parts thereof, especially synchronization. All the possibilities proposed so far involve stopping the processing of the entire unit during reconfiguration. Another problem is selection of the new subconfiguration to be loaded and integration of this subconfiguration into the existing configuration.